1. Field of the Invention
The present invention relates to the field of Semiconductor Integrated Circuits. More specifically, this invention relates to First-In-First-Out (FIFO) memory buffers.
2. Prior Art
A FIFO is often used as a memory buffer between two asynchronous systems with simultaneous read and write access. A first system writes data into the FIFO at one rate and a second system reads data out of the FIFO at a second independent rate. A typical FIFO memory device includes a Random Access Memory (RAM) array and an internal RAM pointer architecture such that there is no fall-through time between a write to a memory location and a read from that memory location. The data rate between the two systems can be regulated by monitoring the status flags and throttling the read and write accesses. Other FIFO memory architectures (e.g. those which do not use a RAM array) also typically include status flags.
To prevent the overflow and loss of data when writing to the memory, and alternatively the reading of false data when reading from the memory, Full and Empty Flags are commonly provided by such memories to halt the writing and reading operations, respectively, until the condition giving rise to the flag has passed by the further reading from or writing to the memory. FIFO flags signal the present condition of a FIFO. An Empty Flag is used to signal when the memory device is empty or not empty. A Full Flag is used to signal when the memory device is full of data or not full of data. The MK4501 memory device, a 512X9 FIFO manufactured by Mostek, is an example of a FIFO memory device having a Full Flag (FF) and an Empty Flag (EF).
In certain applications, the Full and Empty Flags do not provide a system designed with the full flexibility needed, as it may be inconvenient, illogical, or even impossible to immediately stop the writing or reading sequences of the systems connected to the FIFO memory buffer. Therefore, many commercially available FIFO memory devices provide additional status flags such as the Almost Full Flag (AFF) and Almost Empty Flag (AEF) to indicate that the FIFO memory buffer is almost at its full state or almost at its empty state such that writing and reading operations may be more conveniently terminated or initiated as the case may be, before data loss of false data is obtained. To provide even more advanced warning to stop reading and writing operations, many commercially available FIFO memory devices provide half-full flags (HF) to indicate when the FIFO is half full.
It is appreciated that FIFO memory devices currently available generate multiple flag signals to indicate the status of the FIFO at various times. Once a status flag is configured to indicate a particular condition (e.g. half full), that status flag can only be used in that configuration (e.g. half full), unless the status flag is programmable and can be reconfigured upon a RESET signal. In other words, the status flags described above can not be changed dynamically from one configuration to another during the operation of the FIFO memory device. Therefore, separate output flag signals are used to indicate an empty FIFO, a half-full FIFO, a full FIFO or other FIFO conditions, or more than one FIFO flag signal may be combined to indicate a new FIFO condition. With reference to Cypress Semiconductor U.S. Pat. No. 4,888,739, a high HF flag together with a high state Almost Full Empty (AFE) indicates that the memory is almost full, whereas a low HF flag with a high AFE flag will indicate that the memory is almost empty.
Status flags are a desirable feature of FIFO memory devices because they prevent the overflow or loss of data when reading or writing from a FIFO memory device. However, the status flags described above require additional flag logic circuitry and additional output flag pins which increase the die size and the number of outputs of each FIFO integrated circuit.
Therefore, it is advantageous to provide a FIFO memory device that can indicate the condition of the FIFO with reduced flag logic circuitry and flag pins. Furthermore, it is advantageous to poll the FIFO at any time and multiple times during its operation to determine its current condition without waiting for a predetermined status flag to be asserted.